An Optimal Memory BISR Implementation

Although integrated circuits (IC) shrink in size as the fabrication technology progresses, circuit designers always attempt to incorporate as much functionality as possible into a single die. Processor chips, particularly those used in data communications, are known to have the highest transistor density because they contain the highest percentage of embedded memories. In some cases, embedded memories occupy 50-80% of the die area. With inherently high density of memories, the manufacturing yield can become very poor even in a mature process. Also to keep the test cost affordable, having Built-In Self Tests (BIST) for memories is essential although testing would not improve the yield by itself. It has become a common practice to implement some type of memory repair scheme along with BIST in memory dominant IC designs. In this writing, such an integrated scheme is referred as Memory Built-In Self Repair (MBISR.) This paper elaborates a few practical criteria on designing and implementing built-in self-test circuits for testing and repairing a large number of embedded memories of different types and sizes in a single Integrated Circuit (IC). Various test architectures presented in this paper provide for different optimizing criteria such as test time, routing feasibility, silicon overhead, and dynamic power compliance. The repair circuits are based on the most popular and widely accepted built-in-selftest strategy, and are power aware, repair friendly, and supports scan based testing of random glue logic in SOC designs. These features are useful primarily in SOC testing because such designs typically contain many memories that are large but